(a) Field of the Invention
The present invention generally relates to phase locked generators, and more particularly to a phase locked signal generator for generating a square wave signal with a predetermined phase in phase synchronism with (phase locked to) an incoming reference signal which is independent of the period and phase of the square wave signal which is generated from the phase locked signal generator.
(b) Description of Prior Art
Recently, write-in and read-out of a video signal is performed by coupling a digital picture processing apparatus to a video signal recording and reproducing apparatus (hereinafter simply referred to as a VTR). The video signal which is recorded in the VTR, is written into and read out from the digital picture processing apparatus in synchronism with the VTR. In this case, a write-in clock signal or a read-out clock signal which is used to write in or read out the digital picture element information, is phase synchronized with (phase locked to) a horizontal synchronizing signal of the video signal. When one digital picture element information corresponds to one clock pulse of an access clock signal which is used to make access to the digital picture element information, several hundred clock pulses are required with respect to one horizontal scanning line, for example,
As a conventional phase locked signal generator for generating an access clock signal which is phase locked to a reference signal (for example, the horizontal synchronizing signal of the video signal), there is a conventional phase locked signal generator which employs a phase locked loop (PLL). This conventional phase locked signal generator generally comprises a voltage controlled oscillator (VCO), a frequency divider, and a phase comparator. The VCO has an output oscillation frequency which is M times the frequency of the reference signal, where M is an integer. The output oscillation frequency of the VCO is frequency-divided by 1/M in the frequency divider, and an output of the frequency divider is supplied to the phase comparator. The phase comparator compares the phase of the output of the frequency divider with the phase of the reference signal, and supplies an output error voltage to the VCO so as to control the output oscillation frequency of the VCO. The output of the VCO is produced as a clock signal which is phase locked to the reference signal.
However, a horizontal synchronizing signal within a reproduced signal which is obtained from the VTR, constantly includes a jitter. Thus, when such a horizontal synchronizing signal including the jitter is used as the reference signal in the above conventional phase locked signal generator, the phase of the clock signal which is generated from the phase locked signal generator, constantly follows the jitter included in the horizontal synchronizing signal for every period of the horizontal synchronizing signal. Hence, according to the phase locked signal generator employing the PLL, it is impossible to obtain a clock signal having accurate instantaneous phase and frequency, although the phase and frequency are accurate from a statistical viewpoint. For this reason, when the clock signal generated from this conventional phase locked signal generator is used as the access clock signal of the digital picture processing apparatus, the recorded or reproduced picture becomes irregular in the horizontal direction of the picture for every horizontal scanning line. In other words, in the case of the reproduced picture, a straight line which should appear vertical line in the picture may become distorted, for example.
On the other hand, as another example of a conventional phase locked signal generator, there is a phase locked signal generator which assumes a free-running state (asynchronous state) until a reference signal is applied thereto. This conventional phase locked signal generator generates a clock signal which is phase locked to the reference signal, by re-starting the clock signal generation from the time when the reference signal is applied thereto. After the phase locked signal generator re-starts, a clock signal having a constant period is obtained from the phase locked signal generator. Hence, even when the reference signal is a horizontal synchronizing signal including a jitter and the clock pulse is used as the access clock signal of the digital picture processing apparatus, the problem of irregularity in the horizontal direction of the reproduced picture introduced for every horizontal scanning line, is considerably less likely to be introduced compared to the conventional phase locked signal generator which employs the PLL.
However, in the conventional re-start type phase locked signal generator, it is only possible to employ a low-precision oscillator such as an RC oscillator which can change the phase of an output square wave signal responsive to a reference signal by changing the charging timing or the discharge timing of a capacitor. In other words, a high-precision oscillator such as a crystal oscillator which cannot change the phase of an output square wave signal, cannot be employed in the conventional re-start type phase locked signal generator.
As still another example of a conventional phase locked signal generator, there is a phase locked signal generator comprising a crystal oscillator and a counter. An output oscillation frequency of the crystal oscillator is N times the frequency of a desired clock signal, where N is an integer. The counter counts the pulses in the output signal of the crystal oscillator, and essentially frequency-divides the output oscillation frequency of the crystal oscillator by 1/N. The counter is reset by a reference signal, and re-starts the count from the time when the counter is reset. Accordingly, the counter produces a clock signal which is phase locked to the reference signal. However, although the counter produces the clock signal which is phase locked to the reference signal, a phase error is introduced depending on the timing with which the counter is reset. A maximum of this phase error corresponds to one period of the output signal of the crystal oscillator. In order to minimize such a phase error, the output oscillation frequency of the crystal oscillator must be set to a sufficiently high frequency.
However, when the output oscillation frequency of the crystal oscillator is set to a high frequency, a radiation interference is introduced to the outside. Moreover, it becomes difficult to realize the circuit by TTL.